Assessment of Machine Learning Assisted Debugging Approaches in Silicon Validation Workflows
Keywords:
Silicon validation, Machine learning, Debug automation, Failure analysis, Semiconductor designAbstract
The complexity of modern silicon designs necessitates advanced validation strategies to ensure timely product development. Machine Learning (ML) techniques have been increasingly integrated into silicon validation workflows to automate and enhance debugging processes. This paper evaluates different ML-assisted debugging approaches, categorizes their methodologies, and benchmarks their effectiveness. This paper discusses strengths, limitations, and future research directions in the context of real-world silicon validation environments.
References
Khasanov, J., Tan, L., & Tu, Y. (2018). Machine learning for silicon bug localization. Journal of Electronic Testing, 34(2), 123–133.
Gurushankar, N. (2023). Physical verification techniques in advanced semiconductor nodes. ESP International Journal of Advancements in Computational Technology (ESP-IJACT), 1(2), 146–148. https://doi.org/10.56472/25838628/IJACT-V1I2P115
Chatterjee, D., Basu, K., & Bhunia, S. (2017). Post-silicon bug localization using deep learning techniques. Design Automation Conference (DAC).
Zhao, W., Wang, Y., & Xie, Y. (2019). Machine learning in hardware validation: Trends and challenges. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(12), 2345–2358.
Gurushankar, N. (2020). Verification challenge in 3D integrated circuits (IC) design. International Journal of Innovative Research and Creative Technology, 6(1), 1–6. https://doi.org/10.5281/zenodo.14383858
Lobo, J., Mitra, S., & Basu, K. (2017). Machine learning techniques for error detection in post-silicon validation. Microelectronics Journal, 68, 15–24.
Hu, X., Zhang, L., & Huang, M. (2016). Enhancing bug triage with deep learning models. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(7), 2488–2497.
Balasubramanian, A., & Gurushankar, N. (2019). AI-powered hardware fault detection and self-healing mechanisms. International Journal of Core Engineering & Management, 6(4), 23–30.
Jha, S., & Sapatnekar, S. S. (2018). Improving silicon debugging productivity using active learning. International Test Conference (ITC), 1–8.
Bhardwaj, S., Subramanian, A., & Gupta, S. (2019). Learning-driven approaches to failure prediction in complex SoC designs. Integration, the VLSI Journal, 65, 193–204.
Rajan, P., Dey, S., & Kundu, S. (2015). Machine learning based post-silicon fault diagnosis using limited test access. Journal of Electronic Testing, 31(2), 135–146.
Pathak, A., Jain, A., & Chakrabarty, K. (2016). Online learning techniques for post-silicon bug localization in processor cores. Design, Automation & Test in Europe Conference & Exhibition (DATE), 526–531.
Balasubramanian, A., & Gurushankar, N. (2020). Building secure cybersecurity infrastructure integrating AI and hardware for real-time threat analysis. International Journal of Core Engineering & Management, 6(7), 263–270.
Song, L., Chen, Y., & Shen, X. (2017). Data-driven error classification and localization for semiconductor validation. Microprocessors and Microsystems, 52, 238–248.
Wang, L., Kumar, A., & Patil, A. (2019). Predictive failure analysis using recurrent neural networks in silicon debug. IEEE Transactions on Semiconductor Manufacturing, 32(4), 567–576.
Balasubramanian, A., & Gurushankar, N. (2020). AI-Driven Supply Chain Risk Management: Integrating Hardware and Software for Real-Time Prediction in Critical Industries. International Journal of Innovative Research in Engineering & Multidisciplinary Physical Sciences, 8(3), 1–11.
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Copyright (c) 2023 Bala Dharshithan Rajesh (Author)
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
